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--- whats_new [2010/03/04 22:07] – roumani
+++ whats_new [2010/04/19 20:18] (current) – roumani
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 New announcements will be posted here in reverse chronological order.
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+**Mon Apr 19, 10**
+  * The marks of Test #2 and the overall letter grades are now on ePost. The letter grades are based on the weighted sum of the three components: Test1, Test2, and Labs. The breakdown of the Labs component is posted under the 2021L course as before. If you suspect errors in your letter grade, take one of the following actions depending on the type of error: If you see an arithmetic error (i.e. the posted component marks do not add up to the posted letter grade) then email me. On the other hand if you suspect an error in the marking of your second test then wait until the test papers are in the Department Office (around the third week of May) and then request a copy of your exam from the Dept Office and, if needed, submit a petition to the Dept Office.
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+**Wed Mar 31, 10**
+  * Test #2 will be held 7:00-9:00 pm on Thu April 8 in VH-D. //Note that its duration is two hours, not three//. This is a closed-book test with no aids allowed but you may use a calculator. Bring a Photo ID but do not bring any sheets of paper, blank or not (the MIPS green sheet and the needed datapath / control diagrams will be provided). You can write your answers in pen or pencil. Seating may be preassigned and there may be several test versions. No questions will be allowed during the test. The scope of the test is everything that was covered after Test #1, i.e. Hardware and Verilog, the Single-Cycle CPU, Pipelining, and Caches.
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