The weight distribution of the course components is as follows:

• In-class quizzes 10% (2 x 5%)
• Final Exam 30%
• Labs 40% (Lab 1-5 worth 8 marks each)
• Project (Lab 6) 20%

All course components, labs, tests and final, are required. Labs and the quizzes/tests/midterm may only be missed for approved medical reasons. Under these conditions weighting will be redistributed by increasing weighting of the final exam. Labs will be performed in pairs but individual contribution will be assessed.

Students are responsible for all material covered in the lectures, labs and required readings. There is a significant amount of readings for this course. Students are expected to become proficient in Verilog synthesis and microcontroller programming outside of class hours.

You can view your marks here.

Conversion from numeric to letter grade is applied to the overall mark only and in accordance with the following departmental standard:

• Common Grading Scheme for Undergradate Faculties