Components will be given a letter grade mark and then combined to give an overall mark. Numeric marks, when used, will be converted to a letter grade using the standard departmental conversion table.

Classroom participation 8% Tests 48% Labs 44% (Lab 1,2 worth 6 marks each, Labs 3-6 worth 8 marks each)

All course components, labs, test and final, are required. Labs and the midterm may only be missed for approved medical reasons. Under these conditions weighting will be redistributed by increasing weighting of the final exam.

Students are responsible for all material covered in the lectures, labs and required readings. There is a significant amount of readings for this course. Students are expected to become proficient in Verilog synthesis and microcontroller programming outside of class hours.

The weight distribution of the course components is as follows:

• 25% - Assignment 1
• 25% - Midterm
• 25% - Assignment 2
• 25% - Final Exam

You can view your marks here.

Conversion from numeric to letter grade is applied to the overall mark only and in accordance with the following departmental standard:

• Common Grading Scheme for Undergradate Faculties