This lecture covers the design and implementation of the MIPS CPU using a pipeline. This implementation addresses the two main faults of the single-cycle CPU not by eliminating hardware redundancy but by allowing more than one instruction to execute at the same time thereby no hardware unit will be idle. The high latency of the single-cycle approach is also not/ minimized but it is offset by high throughput. Stage balancing, pipeline structure, and hazard detection and avoidance are the key drivers of pipelining.