verilog_modules
Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
verilog_modules [2007/11/16 01:20] – roumani | verilog_modules [2007/11/16 01:29] (current) – roumani | ||
---|---|---|---|
Line 2: | Line 2: | ||
So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves. | So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves. | ||
+ | |||
===== Outline ===== | ===== Outline ===== | ||
- | * Performing PC+4 using the main ALU | + | A Verilog top-level (i.e. '' |
- | * Performing PC+4 + 4*Label using the main ALU | + | |
- | * Adding registers to hold intermediate data | + | * A '' |
- | * Combining | + | * A // |
- | * Issuing the control signals for State #0 | + | * A //circuit// block where all the needed components are instantiated and connected via '' |
- | * Doing something useful | + | * One '' |
- | * Instruction-dependent states | + | * One or more '' |
+ | |||
+ | A Verilog component (i.e. reusable | ||
+ | |||
+ | * The '' | ||
+ | * The declaration section indicates which wire is incoming (by using '' | ||
+ | |||
+ | The functionality of the component can be implemented procedurally (in an '' | ||
+ | |||
+ | |||
+ | |||
Line 23: | Line 35: | ||
===== To Do ===== | ===== To Do ===== | ||
- | * Look at the program '' | + | * Look at the program '' |
- | * Look at the program '' | + | |
+ | * Look at the program '' | ||
verilog_modules.1195176027.txt.gz · Last modified: 2007/11/16 01:20 by roumani