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--- course_outline [2007/07/31 19:53] – external edit 127.0.0.1
+++ course_outline [2012/09/17 02:32] (current) – allison
@@ Line 1: / Line 1: @@
 ====== Course Outline ======
-The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed:
+CSE 3201 Fall 2012
+Department of Computer Science and Engineering
+York University,  Toronto, Ontario
-===== Week 1 =====
-Your notes here.
-===== Week 2 =====
-===== Midterm =====
+[[https://w2prod.sis.yorku.ca/Apps/WebObjects/cdm.woa/22/wo/3jIsgJtbAsIHbBkaBHEQDg/3.1.9.8.3.0.0.5|Fall/Winter 2012-2013 Schedule]]
-===== Drop Deadline =====
-===== Week 13 =====
-===== Final Exam =====
+====== Contact ======
+[[contact | Instructor: R. Allison; TA: Andrew Speers, Jianhui Chen, Navid Mohaghegh]]
+====== Overview ======
+In this course we will cover a series of topics in Digital Logic Design including digital circuit families, Boolean Algebra, minimization, combinational circuits, sequential circuits, registers, counters and memory and register transfer level design. The course and the labs will use Verilog to describe and design circuits.
+====== Prerequisites ======
+Prerequisites: A cumulative grade point average of 4.5 or better over all completed major computer science courses; SC/CSE 2021 4.00; SC/PHYS 3150 3.00 is strongly recommended.
+Students should have a good understanding of electronics and computer organization.
+====== Topics (tentative) ======
+  * Introduction
+  * Boolean algebra
+  * Digital logic implementation
+  * Combinational circuits and optimization
+  * Arithmetic circuits and number systems
+  * Synchronous sequential circuits
+  * Asynchronous sequential circuits (time permitting)
+====== Assigned readings ======
+Chapter 2 all
+Chapter 4.1-4.7, 4.11-4.12
+Chapter 5.1-5.5
+Chapter 6 all
+Chapter 3.1-3.9
+Chapter 7 all
+Chapter 8.1-8.8 (8.9, 8.10 time permitting)
+====== Lectures ======
+[[:lectures:lectures| lecture notes (please login)]]
+====== Evaluation ======
+[[grades| Grades and Grading]]
+====== Laboratory ======
+[[laboratory:start| Lab information]]