course_outline
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====== Course Outline ====== | ====== Course Outline ====== | ||
- | The course outline is a guideline to topics that will be discussed in the course, | + | CSE 3201 Fall 2012 |
+ | Department of Computer Science | ||
+ | York University, | ||
- | ===== Week 1 ===== | ||
- | Your notes here. | ||
- | ===== Week 2 ===== | ||
- | ===== Midterm ===== | + | [[https:// |
- | ===== Drop Deadline ===== | ||
- | ===== Week 13 ===== | ||
- | ===== Final Exam ===== | + | ====== |
+ | |||
+ | [[contact | Instructor: R. Allison; TA: Andrew Speers, Jianhui Chen, Navid Mohaghegh]] | ||
+ | |||
+ | ====== Overview ====== | ||
+ | |||
+ | In this course we will cover a series of topics in Digital Logic Design including digital circuit families, Boolean Algebra, minimization, | ||
+ | |||
+ | ====== Prerequisites ====== | ||
+ | |||
+ | Prerequisites: | ||
+ | |||
+ | Students should have a good understanding of electronics and computer organization. | ||
+ | |||
+ | ====== Topics (tentative) ====== | ||
+ | |||
+ | * Introduction | ||
+ | * Boolean algebra | ||
+ | * Digital logic implementation | ||
+ | * Combinational circuits and optimization | ||
+ | * Arithmetic circuits and number systems | ||
+ | * Synchronous sequential circuits | ||
+ | * Asynchronous sequential circuits (time permitting) | ||
+ | |||
+ | ====== Assigned readings ====== | ||
+ | |||
+ | Chapter 2 all | ||
+ | |||
+ | Chapter 4.1-4.7, 4.11-4.12 | ||
+ | |||
+ | Chapter 5.1-5.5 | ||
+ | |||
+ | Chapter 6 all | ||
+ | |||
+ | Chapter 3.1-3.9 | ||
+ | |||
+ | Chapter 7 all | ||
+ | |||
+ | Chapter 8.1-8.8 (8.9, 8.10 time permitting) | ||
+ | |||
+ | |||
+ | |||
+ | ====== Lectures ====== | ||
+ | |||
+ | [[: | ||
+ | |||
+ | |||
+ | |||
+ | ====== Evaluation ====== | ||
+ | |||
+ | [[grades| Grades and Grading]] | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | ====== Laboratory ====== | ||
+ | |||
+ | [[laboratory: | ||
+ | |||
course_outline.1185911597.txt.gz · Last modified: 2012/09/02 13:36 (external edit)