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--- course_outline [2012/09/14 01:32] – allison
+++ course_outline [2012/09/17 02:32] (current) – allison
@@ Line 36: / Line 36: @@
   * Asynchronous sequential circuits (time permitting)
+====== Assigned readings ======
+Chapter 2 all
-====== Lectures ======
+Chapter 4.1-4.7, 4.11-4.12
-{{:lectures:introduction.ppt.pdf|Introduction}}
+Chapter 5.1-5.5
-{{:lectures:boolean_logic.pdf| Boolean Algebra}}
+Chapter 6 all
+Chapter 3.1-3.9
+Chapter 7 all
+Chapter 8.1-8.8 (8.9, 8.10 time permitting)
+====== Lectures ======
-{{:lectures:verilogsynth.pdf|Verilog overview/refresher}}
+[[:lectures:lectures| lecture notes (please login)]]
-{{:lectures:optimizing_combinational_circuits.pdf|Circuit minimization}}
-[[:lectures:lectures | Lecture notes (login)]]
 ====== Evaluation ======