Differences

This shows you the differences between two versions of the page.

--- course_outline [2007/07/31 19:53] – external edit 127.0.0.1
+++ course_outline [2013/09/17 19:44] (current) – magiero
@@ Line 1: / Line 1: @@
 ====== Course Outline ======
-The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed:
+===== Staff =====
-===== Week 1 =====
+[[Contact | Instructor: Sebastian Magierowski]]
-Your notes here.
+[[Contact | Teaching Assistants: Syed Zahidul Islam, Giancarlo Ayala-Charca]]
-===== Week 2 =====
-===== Midterm =====
+===== Overview =====
-===== Drop Deadline =====
+In this course we will cover a series of topics in Digital Logic Design including digital circuit families, Boolean Algebra, minimization, combinational circuits, sequential circuits, registers, counters and memory and register transfer level design. The course and the labs will use Verilog to describe and design circuits.
-===== Week 13 =====
+===== Mark Breakdown =====
+Labs: 15%
+[[Important Dates | Assignments]]: 10%
+[[Important Dates | Midterm]]: 25%
+Final: 50%
+===== Textbook Readings =====
+From the [[Textbook | Brown/Vranesic 3/e Text]]
+  * Ch. 1
+  * Ch. 2
+  * Ch. 3
+  * Ch. 4
+  * Ch. 5
+  * Ch. 6
+  * App. B
+===== Lectures =====
+[[lectures: | Lecture Notes (please log in)]]
-===== Final Exam =====