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course_outline

Course Outline

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Overview

In this course we will cover a series of topics in Digital Logic Design including digital circuit families, Boolean Algebra, minimization, combinational circuits, sequential circuits, registers, counters and memory and register transfer level design. The course and the labs will use Verilog to describe and design circuits.

Mark Breakdown

Labs: 15%

Assignments: 10%

Midterm: 25%

Final: 50%

Textbook Readings

From the Brown/Vranesic 3/e Text

  • Ch. 1
  • Ch. 2
  • Ch. 3
  • Ch. 4
  • Ch. 5
  • Ch. 6
  • App. B

Lectures

course_outline.txt · Last modified: 2013/09/17 19:44 by magiero