assignments:a4
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| assignments:a4 [2017/12/05 22:16] – created aboelaze | assignments:a4 [2017/12/12 22:28] (current) – aboelaze | ||
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| * 4.16 | * 4.16 | ||
| * 4.20 | * 4.20 | ||
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| + | 4.3 -- 35% 100% 76% It is always producing the sign extended number needed or not | ||
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| + | 4.5 -- The instruction is sd x12, 20(x1) | ||
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| + | 4.5-1 -- 00 and 0010 ( we did not cover this in details) | ||
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| + | 4.5-2 -- PC+4 | ||
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| + | 4.5-3 -- ALUsrc inputs are Reg[x12] and immediate output is immediate (0x0000000000000014) | ||
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| + | 4.5-4 -- ALU inputs Reg[x12] and immediate | ||
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| + | 4.7 -- 700, 950, 905, 705, 700 , 905 psec. | ||
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| + | 4.8 -- 1.174 | ||
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| + | 4.13 -- need MUX's and paths to these mux's | ||
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| + | 4.16 -- | ||
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| + | 4.16.1 Pipelined: 350; non-pipelined: | ||
| + | 4.16.2 Pipelined: 1750; non-pipelined: | ||
| + | 4.16.3 Split the ID stage. Th is reduces the clock-cycle time to 300ps. | ||
| + | 4.16.4 35%. | ||
| + | 4.16.5 65% | ||
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| + | 4.30 -- | ||
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| + | addi x11, x12, 5 | ||
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| + | NOP | ||
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| + | NOP | ||
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| + | add x13, x11, x12 | ||
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| + | addi x14, x11, 15 | ||
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| + | NOP | ||
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| + | add x15, x13, x12 | ||
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