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assignments:start

Lab Assignments

You will have 8 lab assignments that you are going to do in your lab sessions. 4 before the midterm and 4 after the midterm and up to your final. There will be one make-up assignment for each of those 4 for which those you missed only a single lab can request to do as a make-up.

On each Labs's day, the lab will be accessible after the prelab period of about 90m. You must be physically in LAS1006 and using one of the workstation in the room. Click on the above link to reveal the lab question. If any problem, reload the page. Ask the TA for assistance if the problem persists.

Important: The workstations in LAS1006 will be switched to labtest mode 90 minutes after the start of the lab. A warning message will be shown on the workstation screens 80 minutes after the start of the lab. The prelab submissions completed BEFORE the warning message shows on the screen will be made available to you during the labtest in read-only mode in the unsubmit directory in your home directory.

Note that in labtest mode, you will have access to the software on the EECS systems and the course labtest web site, but will lose access to all of the files in your home directory, sending and receiving e-mail, printing, the external web, USB key/cdrom/floppy access, existing temporary files stored on the machine, and all access to the Internet including access to other EECS machines and other York services like Moodle.

RISC-V Green Card

RVS Simulator

For Labs A-D we will use the RISC-V Visual Simulator (RVS) on the workstations in LAS1006. The current version of the RVS simulator can be invoked by typing rvs in a terminal window.

You can also download the latest version of RVS (046) for your own personal use at home here:

RVS Linux

RVS Mac

RVC Windows

RVX Simulator

Verilog Labs

For Labs K-N, we will use Icarus Verilog on the workstations in LAS1006. Type iverilog in a terminal window to invoke the Icarus Verilog compiler. Type vvp in a terminal window to run the compiled program.

Verilog Quick Reference Card

Verilog Mini reference

verilog Reference Guide

Sequential component library modules for Labs M and N

Icarus Verilog Download

Labs (Available on its day)

Here, you can link to your course assignments and they will be posted gradually.

  • MIDTERM
Submissions

Submit the prelabs (the examples and the exercises in the lab book) right after you save your work in a file as instructed, using the following command (change PreA and a1a.asm as needed):

submit 2021 PreA a1a.asm

Submit the the lab assignment (your solution to the secret question revealed in the middle of the lab time) by the end of the current lab as instructed, using the following command (change LabA01 and aas5a.asm as needed):

submit 2021 LabA01 aas5a.asm

Important: If you misss a lab you will get 0 points unless you do the makeup for the missed lab. You are allowed to do ONE makeup lab out of A, B, C, and D, and ONE makeup lab out of K, L, M, and N. For any additional missed lab, the procedure for a missed test (see the Tests section) will apply.

assignments/start.txt · Last modified: 2019/09/12 13:45 by aashouri