Check the eclass

lab_1.pdf

LAB 3

lab_3.pdf

The Verilog code should be according to the following prototype. It will be submitted separately using submit or websubmit

module trafficlight(

input rst, / / resets the system to the initial state (main road green

input request,

input clk,

output reg [5:0] light,

output reg [7:0] sevseg

);

endmodule