Check the eclass

lab_1.pdf

LAB 2

LAB 3

The Verilog code should be according to the following prototype. It will be submitted separately using submit or websubmit

module trafficlight (

input rst, / / resets the system to the initial state (main road green

input request, / / car sensor ored with pedestrian request

input clk, / / system clock

output reg [5:0] light, / / MainG MainY MainR SecG SecY SecR

output reg [7:0] sevseg / / dot g f e d c b a

);

endmodule

LAB 4

Her is LAB 5 due March 21

{{:lab_6_2021.pdf|}LAB 6}