Differences

This shows you the differences between two versions of the page.

--- cadenceuniversityprogram [2014/04/21 14:54] – magiero
+++ cadenceuniversityprogram [2019/02/28 14:57] (current) – magiero
@@ Line 2: / Line 2: @@
 ===== Cadence University Program Member =====
+{{cadencelogo.gif}}
 This page provides information only about the Cadence software used at York University.
@@ Line 9: / Line 11: @@
 === Cadence Tools in Our Research ===
-A wide variety electronics research at York employs the Cadence products in the design of its electronic technology.  Areas of research at York where Cadence tools are used include:
+A wide variety electronics research at York employs the Cadence products in the design of its electronic technology.  Areas of research at York where the wide variety of Cadence tools (Custom IC, Digital IC, Verification) are used include:
+• Hardware accelerated machine learning\\
+• Wearable computing\\
 • Radio frequency integrated circuits (RFICs)\\
 • High-speed wireline systems\\
@@ Line 21: / Line 25: @@
 === Cadence Tools in Our Curriculum ===
-EECS 4612: Digital VLSI (coming soon)
+EECS 3610: Semiconductor Physics and Devices (Winter 2019, Winter 2020)\\
+EECS 3611: Analog IC Design (Winter 2019 Winter 2020)\\
+EECS 4611: Advanced Analog IC Design (Winter 2020)\\
+EECS 4612: Digital VLSI (Winter 2019, Winter 2020)\\
+EECS 6505: Physical and Systems Design Issues in ASICs (Winter 2020)
-This course deals with the electrical engineering issues of microchip design.  Students employ a variety of Cadence tools to complete their designs including:
+These courses deal with the electrical engineering issues of microchip design.  Students employ a variety of Cadence tools to complete their designs including:
-• Virtuoso Layout Suite\\
+• Virtuoso Layout Suite for **Custom ICs** and **Digital ICs**\\
-• Virtuoso Multi-mode Simulation Option\\
+• Virtuoso Multi-mode Simulation Option for **Custom ICs**\\
-• Cadence Chip Assembly Router\\
+• Cadence Chip Assembly Router for **Digital ICs**\\
-• Cadence Simulation Analysis Environment\\
+• Cadence Simulation Analysis Environment for **Verfication**\\
-• Encounter Digital Implementation System\\
+• Encounter Digital Implementation System  for **Digital ICs**\\
-• Encounter RTL Compiler
+• Encounter RTL Compiler for **Digital ICs**
 === Disclaimer ===
@@ Line 44: / Line 52: @@
 == ==
-//This webpage is maintained by Sebastian Magierowski//
+//This webpage is maintained by Sebastian Magierowski//\\
-//Last updated: April 20, 2014//
+//Last updated: March 01, 2019//
 **Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134.**