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Synopsys provides a bunch of Tcl scripts as part of their reference methodology (rm) offering. An incomplete view into this flow for the ICC tool is shown below.

• icc_setup.tcl (in rm_setup): Whole bunch of ICC variables set.
  • make_generated_vars.tcl: Generated in the Makefile and defines some basic stuff.
  • common_setup.tcl (in rm_setup): Basic definitions like VDD and VSS.
  • set_mw_lib_reference $MW_DESIGN_LIBRARY -mw_reference_library *
  • check_icc_rm_values.tcl (in rm_icc_scripts): Exits ICC if script error.
    
• open_mw_cel
  
• initialize_floorplan: Make an initial floorplan.
  
• $ICC_PHYSICAL_CONSTRAINTS_FILE (optional)
  
• common_optimization_settings_icc.tcl (in rm_icc_scripts)
  
• common_placement_settings_icc.tcl ( in rm_icc_scripts)
  
• derive_pg_connection
  
• save_mw_cell

• icc_setup.tcl (in rm_setup): Called at the beginning of all scripts.
• proc_explore.tcl (in rm_icc_dp_scripts)
  • dp_explore
  • set_host_options
  • set_fp_placement_strategy
  • create_fp_placement
  • synthesize_fp_rail
  • commit_fp_rail
  • create_fp_virtual_pad (optional)
  • analyze_fp_rail
  • optimize_fp_timing
  • route_zrt_global OR route_global
  • remove_route_by_type
  • extract_rc
  • create_qor_snapshot
  • report_timing
  • report_qor_snapshot
  • write_floorplan
  • write_pin_pad_physical_constraints
  • write_def
• gui_set_current_task
• common_optimization_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_placement_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• ONE OF: macro_placement_exploration_dp.tcl OR baseline.tcl (both in rm_icc_dp_scripts), for baseline…
  • create_fp_placement: Place the standard cells in your boundary.
  • route_fp_proto
  • save_mw_cell
  • remove_route_by_type
  • extract_rc
  • create_qor_snapshot
  • synthesize_fp_rail: Synthesize the power rails. Can see estimated rail voltage drops.
  • commit_fp_rail: Commit power plan if power budget is met.
  • analyze_fp_rail
  • common_optimization_settings_icc.tcl
  • extract_rc
  • report_timing
  • optimize_fp_timing
  • route_fp_proto
  • save_mw_cel
  • remove_route_by_type
  • extract_rc
  • create_qor_snapshot
  • report_qor_snapshot
  • report_timing
  • set_dont_touch_placement
  • save_mw_cel
  • write_floorplan
  • write_pin_pad_physical_constraints

• icc_setup.tcl (in rm_setup): Called at the beginning of all scripts.
  
• common_optimization_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_placement_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_cts_settings.tcl (in rm_icc_scripts): Clock tree synthesis. Set in place_opt and clock_opt sessions.
  
• open_mw_lib
  
• copy_mw_cel
  
• open_mw_cel
  
• place_opt
  
• derive_pg_connection
  
• save_mw_cell

• icc_setup.tcl (in rm_setup)
  
• open_mw_lib
  
• copy_mw_cel
  
• open_mw_cel
  
• common_optimization_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_placement_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_cts_settings.tcl (in rm_icc_scripts): Clock tree synthesis. Set in place_opt and clock_opt sessions.
  
• set_app_var
  
• set_delay_calculation
  
• clock_opt -only_cts -no_clock_route: Perform clock tree synthesis.
  
• derive_pg_connection
  
• common_post_cts_timing_settings.tcl (in rm_icc_scripts)
  
• remove_ideal_network
  
• set_fix_hold
  
• save_mw_cel

• icc_setup.tcl
  
• open_mw_lib
  
• copy_mw_cel
  
• open_mw_cel
  
• common_optimization_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_placement_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_cts_settings.tcl (in rm_icc_scripts): Clock tree synthesis. Set in place_opt and clock_opt sessions.
  
• common_post_cts_timing_settings_icc.tcl (in rm_icc_scripts)
  
• set_app_var
  
• extract_rc
  
• clock_opt -no_clock_route -only_psyn -area_recovery
  
• route_group
  
• derive_pg_connection
  
• same_mw_cel

• icc_setup.tcl (in rm_setup)
  
• open_mw_lib
  
• copy_mw_cel
  
• open_mw_cel
  
• common_optimization_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_placement_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_cts_settings.tcl (in rm_icc_scripts): Clock tree synthesis. Set in place_opt and clock_opt sessions.
  
• common_post_cts_timing_settings.tcl
  
• common_route_si_settings_icc.tcl (in rm_icc_scripts)
  
• set_si_options: Turn off SI for clock routing
  
• set_delay_calculation
  
• set_route_mode_options
  
• optimize_clock_tree
  
• derive_pg_connection
  
• save_mw_cel

• icc_setup.tcl (in rm_setup)
  
• open_mw_lib
  
• copy_mw_cel
  
• open_mw_cel
  
• common_optimization_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_placement_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_cts_settings.tcl (in rm_icc_scripts): Clock tree synthesis. Set in place_opt and clock_opt sessions.
  
• common_post_cts_timing_settings.tcl
  
• common_route_si_settings_icc.tcl (in rm_icc_scripts)
  
• set_route_mode_options: Load route and SI settings.
• report_preferred_routing_direction: Check routability.
• report_tlu_plus_files
• route_opt -initial_route_only -num cpus *: Initial route. CPU count can be set to 1 as a minimum.
• update_clock_latency

• icc_setup.tcl (in rm_setup)
  
• open_mw_lib
  
• copy_mw_cel
  
• open_mw_cel
  
• common_optimization_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_placement_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_post_cts_timing_settings.tcl (in rm_icc_scripts)
  
• common_route_si_settings_icc.tcl (in rm_icc_scripts)
  
• set_app_var compile_instance_name_prefix icc_route_opt: Start post route optimization.
  
• set_route_mode_options -zroute false
  
• route_opt -skip_initial_route -effort * -xtalk_reduction: effort can be set to “low”
  
• derive_pg_connection
  
• save_mw_cel

• icc_setup.tcl (in rm_setup)
  
• open_mw_lib
  
• copy_mw_cel
  
• open_mw_cel
  
• common_optimization_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_placement_settings_icc.tcl (in rm_icc_scripts): In all scripts.
  
• common_post_cts_timing_settings.tcl (in rm_icc_scripts)
  
• common_route_si_settings_icc.tcl (in rm_icc_scripts): Loads the route and SI settings.
  
• set_droute_options -name doAntennaConx -value 4: Antenna fixing.
  
• report_antenna_rules: Antenna fixing
  
• route_search_repair -rerun_drc -loop 10: Antenna fixing.
  
• report_antenna_ratio: Antenna fixing
  
• insert_diode -no_auto_cell_selection -diode_cells *: Antenna fixing.
  
• route_search_repair -rerun_drc -loop 3: Antenna fixing.
  
• report_antenna_ration: Antenna fixing.
  
• route_spreadwires: Wire spreading for shorts.
  
• route_widen_wire: Wire widening for opens.
  
• set_app_var droute_optViaTimingDriven 1: Timing driven redundant via insertion.
  
• interst_redundant_vias -auto_mode insert -num_cpus *
  
• insert_stdcell_filler -cell_without_metal $FILLER_CELL -connect_to_power “VDD” -connect_to_ground “VSS”: $FILLER_CELL defined in make_generated_vars.tcl.
  
• route_opt -incremental -size_only: Incremental timing optimization.
  
• route_search_repair -rerun_drc -num_cpus 1 -loop 2
  
• derive_pg_connection
  
• save_mw_cel

• icc_setup.tcl (in rm_setup)
  
• open_mw_cel metal_fill_icc -lib *_LIB
  
• change_names -rules verilog -hierarchy
  
• save_mw_cel -as change_names_icc
  
• close_mw_cel
  
• open_mw_cel change_names_icc
  
• write_verilog -diode_ports -no_physical_only_cells *.output.v
  
• write_verilog -no_physical_only_cells *.output.dc.v
  
• write_verilog -diode_ports -pg *.output.pg.lvs.v
  
• set_app_var write_sdc_output_lumped_net_capacitance false
  
• set_app_var write_sdc_output_net_resistance false
  
• write_sdc *.output.sdc
  
• extract_rc -coupling_cap
  
• write_parasitics -format SBPF -output *.output.sbpf
  
• write_def -output *.output.def
  
• save_mw_cel
  
• close_mw_cel
  
• open_mw_cel
  
• create_ilm -include_xtalk
  
• create_macro_fram
  
• set_droute_options -name doAntennaConx -value 4
  
• extract_hier_antenna_property -cell_name *
  
• close_mw_cel

1. initialize_floorplan (create_floorplan): In /rm_icc_scripts/init_design_icc.tcl Here you can set how close the design comes to your i/o pins.
   
2. create_rectilinear_rings (in Preroute → Create Rings…)