This lecture covers the design and implementation of the MIPS CPU using a pipeline. This implementation addresses the two main faults of the single-cycle CPU not by eliminating hardware redundancy but by allowing more than one instruction to execute at the same time thereby no hardware unit will be idle. The high latency of the single-cycle approach is also not minimized but it is offset by high throughput. Stage balancing, pipeline structure, and hazard detection and avoidance are the key drivers of pipelining.

• The pipelining concept, balancing, and latency versus throughput
• The need for pipeline registers
• The MIPS ISA is designed to eliminate structural hazards
• Data hazards and forwarding
• Inserting a bubble into a pipeline
• Handling branch hazards
• Delayed branching and populating the delay slot

• One can increase throughput despite an increase in latency
• For a process to be pipelined, the stages must be balanced and no structural violations should be allowed
• Dependencies tend to lower the pipeline's throughput

• Pipelining

• Read Sections 6.1 through 6.7 of the textbook.
• Do the pipeline exercises (in the Resources page).