CSE3201

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====== Laboratory ======



[[:policies| See here for important policies on laboratory requirements, submission and evaluation]]

The laboratory is hands on and students should have experience with electronic circuits and computer organization and digital logic (e.g. strongly recommended or prerequisite courses are Phys 3150 and CSE 2021).

Some useful information and examples for the DE2 board are availble from [[http://www.altera.com/education/univ/materials/digital_logic/unv-overview.html| Altera]]


====== Lab documentation ======


[[:resources]]

The DE2 user manual is [[http://www.cse.yorku.ca/course_archive/2011-12/F/3201/DE2_UserManual.pdf|here (manual)]] and here is the [[http://www.cse.yorku.ca/course_archive/2011-12/F/3201/DE2_pin_assignments.csv|DE2 pin assignment file]]


====== Location ======


This course will make use of the digital systems lab in LAS1004. The lab is equipped with boards and supporting software and equipment for development of Altera CPLD designs.


TA office hours. Every Friday 11:00-13:00 in the lab.

====== Lab Exercises ======

{{:lectures:lab_report_guidlines.pdf|Report Guidelines}}

  * Tutorials for Lab 1 {{:2_tut_quartus_intro_verilog.pdf|Verilog tutorial}} and {{:3_tut_quartus_intro_schem.pdf|Schematic capture tutorial}}. Note the simulation procedure is a little different in the latest version of Quartus. Please see {{:quartus_ii_simulation.pdf|this document}}.

{{:lectures:cse3201_lab2_f12.pdf|Lab 2 (corrected)}}

{{:lectures:cse3201_lab3_f12.pdf| Lab 3}}


{{:lectures:cse3201_lab4_f12.pdf|Lab 4}}

{{:lectures:lab5_3201f12.pdf|Lab 5}}

{{:tutorial_quartusii_timing_simulation_verilog.pdf| Timing simulation tutorial}}

{{:tut_signaltapii_verilogde2.pdf|Signal Tap Tutorial}}

{{:lectures:cse3201_lab6_f12.pdf|Lab 6}}  For pre-lab please read the Timing simulation tutorial and the Signal Tap Tutorial.

{{:lectures:lab7_3201f12.pdf|Lab 7}}

{{:lectures:cse3201_lab8_f12.pdf|Lab 8}}

{{:lectures:cse3201_lab9_f12.pdf| Lab 9}}