Due Wed. Oct. 16 at end of class.

Hand in Questions:

1. 2.39 state the cost for both SOP and POS (assume true and false of input variables are free)
2. 2.45*
3. 2.48*
4. 2.49
5. Show the transistor-level circuit schematic for a 3-input CMOS AND gate.
6. 2.53
7. 2.54*
8. 2.55
9. 2.56*
10. 2.57
11. Write valid Verilog code for an 8:1 multiplexer “mod8” with inputs x[7:0] and output y.
12. 2.69