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Assignment 2

Due Wed. Oct. 16 at end of class.

Hand in Questions:

2.39 state the cost for both SOP and POS (assume true and false of input variables are free)
2.45*
2.48*
2.49
Show the transistor-level CMOS circuit schematic (NOT the gate schematic) implementing a 3-input AND gate (AND3).
2.53
2.54*
2.55
2.56*
2.57
Write valid Verilog code for an 8:1 multiplexer “mod8” with inputs x[7:0] and output y.
2.69
2.74
3.1*
3.2*
3.3*
3.4*
3.5
3.11*
3.13*