course_outline
This is an old revision of the document!
Table of Contents
Course Outline
The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed:
Staff
Instructor: Sebastian Magierowski
Teaching Assistants: Syed Islam, Giancarlo Ayala-Charca
Overview
In this course we will cover a series of topics in Digital Logic Design including digital circuit families, Boolean Algebra, minimization, combinational circuits, sequential circuits, registers, counters and memory and register transfer level design. The course and the labs will use Verilog to describe and design circuits.
course_outline.1378739362.txt.gz · Last modified: 2013/09/09 15:09 by magiero