This lecture covers the design and implementation of the MIPS CPU using a multi-cycle approach. This implementation addresses the two main faults of the single-cycle CPU by eliminating hardware redundancy on the chip and starting the next instruction immediately after the current one completes its execution (rather than waiting a fixed amount of time based on the slowest instruction).

• Performing PC+4 using the main ALU
• Performing PC+4 + 4*Label using the main ALU
• Adding registers to hold intermediate data
• Combining the two memory units
• Issuing the control signals for State #0
• Doing something useful in State #1
• Instruction-dependent states

• Using a variable CPI (Cycle Per Instruction) to address the “catering for the slowest” criticism.
• Merging hardware units to address the “redundant, and thus too hot hardware” criticism.

• The Mutil-Cycle CPU

• Early release of the Pipelining Lecture notes

• Read Section 5.5 of the textbook (5.4 in the old edition).
• Do the multi-cycle exercises accessible through the Resource page.