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Table of Contents
Labs
Lab 6: Timing Measurements
Lab 5: Multipliers
Lab Date: Mon. Oct. 28, 2013 in LAS 1004A
Implement multipliers using a couple different adder arrangements.
Lab 4: Number Systems
Lab 3: Seven Segment Displays
Lab Date: Mon. Oct. 7, 2013 in LAS 1004A
Writing Verilog code to control the seven-segment display on your DE2.
Lab 2: Boolean Logic and Digital Circuits
Lab Date: Mon. Sept. 30, 2013 in LAS 1004A
Writing a variety of Verilog modules for the DE2 implementing a parity function as well as a parity checker. Make sure to do your prelab (see Lab 2 description below).
Lab 1: Verilog/Schematic Design Entry Tutorial
Lab Date: Mon. Sept. 23, 2013 in LAS 1004A
An introduction to FPGA programming on the DE2 Development System (see DE2 Documentation below for more info). You'll be doing both Verilog and Schematic entry. Please read both documents ahead of time.
Verilog Entry on Quartus II 12.1 (updated Sept. 18, 2013)
Schematic Entry on Quartus II 12.1 (updated Sept. 18, 2013)
Each of these two tutorials asks you to go from “Starting a New Project” to “Testing the Designed Circuit” you must demonstrate a working circuit (obtained from both a Verilog and Schematic starting point) by the end of the lab to get full marks. If you read ahead this should be easy and will effectively serve as your prep points (if you don't read the documents above before the lab you will find it hard to finish).