Lab Date: Mon. Nov. 4, 2013 in LAS 1004A

Create test vectors for your multiplier (from Lab 5) and verify its operation more thoroughly using Altera's system-level debugging tool, SignalTap. Links on Altera timing and SignalTap below (recommended to go over these before Lab 6).

Lab 6

Timing Simulations

Signal Tap

Lab Date: Mon. Oct. 28, 2013 in LAS 1004A

Implement multipliers using a couple different adder arrangements.

Lab 5

Lab Date: Mon. Oct. 21, 2013 in LAS 1004A

Displaying BCD numbers and adding them up.

Lab 4

Lab Date: Mon. Oct. 7, 2013 in LAS 1004A

Writing Verilog code to control the seven-segment display on your DE2.

Lab 3

Lab Date: Mon. Sept. 30, 2013 in LAS 1004A

Writing a variety of Verilog modules for the DE2 implementing a parity function as well as a parity checker. Make sure to do your prelab (see Lab 2 description below).

Lab 2

Lab Date: Mon. Sept. 23, 2013 in LAS 1004A

An introduction to FPGA programming on the DE2 Development System (see DE2 Documentation below for more info). You'll be doing both Verilog and Schematic entry. Please read both documents ahead of time.

Verilog Entry on Quartus II 12.1 (updated Sept. 18, 2013)

Schematic Entry on Quartus II 12.1 (updated Sept. 18, 2013)

Each of these two tutorials asks you to go from “Starting a New Project” to “Testing the Designed Circuit” you must demonstrate a working circuit (obtained from both a Verilog and Schematic starting point) by the end of the lab to get full marks. If you read ahead this should be easy and will effectively serve as your prep points (if you don't read the documents above before the lab you will find it hard to finish).

DE2 Manual

DE2 Pin Assignment File

DE2 Pin Table (just the file above, but in table format)

Verilog Tutorial

Verilog Quick Reference

Verilog Coding Style