The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed:
Introduction
Basic Concepts + Review of Numbering Systems
Logic Gates and Basic Logic Circuits
Introduction to Verilog HDL
Boolean Algebra
Karnaugh Maps and Basic Arithmetic Circuits
Multipliers, Multiplexers, Decoders, and RAM
ROMs, PLDs, and ALUs
Introduction to Sequential Circuits
Analysis of Sequential Circuits
Design of Sequential Circuits + Guidelines for Midterm
Registers and Counters
Synthesis-Friendly Verilog
Modular Design + ASM's
Design with MUX's
Pipelining
Fast Adders I
Fast Adders II
Read this well while studying for final exam