course_outline

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Course Outline

The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed:

Lecture 1

Lecture 2

Basic Concepts + Review of Numbering Systems

Lecture 3

Logic Gates and Basic Logic Circuits

Lecture 4

Introduction to Verilog HDL

Lecture 5

Boolean Algebra

Lecture 6

Karnaugh Maps and Basic Arithmetic Circuits

Lecture 7

Multipliers, Multiplexers, Decoders, and RAM

Lecture 8

ROMs, PLDs, and ALUs

Lecture 9

Introduction to Sequential Circuits

Lecture 10

Analysis of Sequential Circuits

Lecture 11

Design of Sequential Circuits + Guidelines for Midterm

Midterm

Lecture 12

Registers and Counters

Lecture 13

Synthesis-Friendly Verilog

Lecture 14

Modular Design + ASM's

Lecture 15

Design with MUX's

Lecture 16

Lecture 17

Lecture 18

{{:eecs3201_guidelines_final_exam.pdf|Guidelines for Final Exam}}

Final Exam

course_outline.1418235781.txt.gz · Last modified: 2014/12/10 18:23 by iamer