The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed:

Chapter 1 Introduction

Assigned reading 1.1 1.2 1.3

for Wed. class 1.5, 1.6 1.7

Assignment 1 is out, check the Assignments tab

Assembly language three slides per page and One slide per page

Assigned reading 2.1 2.2 2.3

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Instruction format 1 slide per page and 3 slides per page

Assigned reading 2.4 (review) 2.5 2.6 2.7 2.8

Procedure call 1 slide per page and 3 slides per page

Lab C check Labs page

The lab demo will be limited to C1 to C6 only, C7 and C8 could be demoed the following lab.

Quiz 1 (Wednesday) Quiz 1 covers up to (not including) procedure call

Lab Test Monday is Thanksgiving no classes

The slides for synchronization and linking 2 slides per page and 3 slides per page

Section 2.11, 2.12, 2.16-2.19

Lab Project

The lab is due Nov. 2nd

MIDTERM Midterm covers up to and including section 2.7

a brief introduction to Verilog

The midterm is on Wednesday

and Lab test 1

Chapter 3: review of integer representation integer_rep.pdf

floating point Introduction to Floating Point Numbers

Lab project

FP addition and multiplication

FP Implementation

Lab K

The processor Introduction and building the datapath

Quiz 2 quiz 2 covers 2.7, 2.8, 3.1 and 3.2

Start in Chapter 4 we will cover 4.1-4.10 parts of 4.11 (see class notes) and 4.14

Lab L

Some of you asked about the solution of one particular problem in the labtest, here is the solution. Please note that is ONE possible solution, there are many other ways to do this.

here is the solution for group A and B

Here is lab test M1 test cases: Q1 3 5 , 3 -4, -6 2, -5 -9 Q2 4, 3, 5, 2 Q3 6,2, 15, 22

Here is lab test M2 test cases: Q1 3 5, 3 -4, -6 2, -5 -9, Q2 1 2, 3 0, 0 3, 4 7 Q3 6, 2, 15, 22

Here is lab test T1 test cases: Q1 3 5, 3 -4, -6 2, -5 -9 Q2 3 5, -3 5, 0 3, -3 -5 Q3 5, 2, 15, 8

Here is lab test T2 test cases: Q1 3 5 , 3 -4, -6 2, -5 -9, Q2 3 5, -3 5, 0 3, -3 -5 Q3 5, 2, 15, 8

I have sent to you the labtest files you submitted on your cse (eecs) account. Please check your account and check the test cases I posted earlier

LAB M

LAB N

Lab N (cont.) only for one hour

lab test 2 Labtest will cover Verilog

Quiz 3